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«By SIDDHARTH CHOUKSEY A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE ...»

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MODELING, DESIGN, AND PERFORMANCE OF NANOSCALE DOUBLE-GATE CMOS

By

SIDDHARTH CHOUKSEY

A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL

OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT

OF THE REQUIREMENTS FOR THE DEGREE OF

DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA

© 2009 Siddharth Chouksey To my family, friends, and the almighty

ACKNOWLEDGEMENTS

Being where I am today is literally a dream come true. I believe success happens when talent meets an opportunity. Numerous opportunities came my way, many times indirectly and disguised, that made all this possible. I do not know what made those opportunities come my way, if not, the supreme force guiding our lives - God. Therefore, first of all I would like to thank God for making this Ph.D. a part of his plan. I do not think its within my capability to fully express my sense of awe and gratitude toward my advisor, Dr. Jerry G. Fossum. Working with him has been a tremendous learning experience from me. He taught me not only through the classes, feedbacks, and discussions, but many times when he was not even intending! I have learned a lot just by watching him work; his enthusiasm for work, patience, and analytical skills are exemplary. I thank Dr. Fossum for his support and guidance throughout my work. I would like to thank Dr. Scott Thompson, Dr. Jing Guo, and Dr. Selman Hershfield for agreeing to be on my committee as well as for helpful discussions during my research work. I would like to acknowledge Freescale Semiconductor for their support, and thank Intel Corp. for giving me opportunity to intern with them twice. I would like to thank my mother for her undiminished confidence in me, and for all her prayers. I will not be surprised if this Ph.D. means more to her than what it means to me. I would like to thank my father for his support, and my brother, sister-in-law, sister, brother-in-law, my niece and nephew for their encouragement. I was fortunate to have Murshed Chowdhury, Shishir Agrawal, Zhichao Lu, Zhenming Zhou, Weimin Zhang, Sueng-Hwan Kim, and Dabraj Sarkar as my colleagues. I would like to thank them for all the help they extended to me throughout my work. I would like to thank my numerous friends, in and out of Gainesville, for their companionship through these years.

TABLE OF CONTENTS

page ACKNOWLEDGEMENTS

LIST OF TABLES

LIST OF FIGURES

LIST OF ABBREVIATIONS

ABSTRACT

CHAPTER

1 INTRODUCTION

2 DICE: A BENEFICIAL SHORT-CHANNEL EFFECT IN DOUBLE-GATE

MOSFETs.......

2-1 Introduction

2-2 Modeling

2-3 Model Corroboration and Predicted DICE Impacts

2-4 Summary

3 THRESHOLD VOLTAGE ADJUSTMENT IN NANOSCALE DG FINFETS VIA

LIMITED SOURCE/DRAIN DOPANTS IN THE CHANNEL

3-1 Introduction

3-2 S/D Doping-Dependent Vt

3-3 Demonstration and Verification of Design Approach

3-4 Sensitivity and RDF Analyses

3-5 Summary

4 PHYSICAL INSIGHTS ON ANALOG/RF PERFORMANCE OF DOUBLE-GATE

FINFETS, WITH COMPARISION TO BULK-SILICON MOSFETS

4-1 Introduction

4-2 Device Characteristics

4-3 RF FinFET Scaling

4-4 Summary

5 INSIGHTS ON DESIGN AND SCALABILITY OF THIN-BOX FD/SOI CMOS............68

5-1 Introduction

5-2 LP Devices

5-3 HP Devices

5-4 Comparisons with FinFETs

5-5 Conclusions

6 SUMMARY AND FUTURE WORK

6-1 Summary

6-2 Future Work

APPENDIX

UFDG MODEL REFINEMENTS

A-1 Introduction

A-2 Strong-Inversion Intrinsic Charge Modeling

A-3 Weak-Inversion Inner Fringe Charge Model

A-4 DIBL-Dependent Definition of VTW

LIST OF REFERENCES

BIOGRAPHICAL SKETCH

–  –  –

2-1 UFDG-predicted DICE and DIBL in an Lg = 18nm nMOSFET with varying UTB thickness, with and without a 2nm gate-source/drain underlap

Medici-predicted sensitivity of Ioff to variations in σL of NSD(y) in the Lg = 18nm LP and 3-1 HP DG FinFETs

3-2 Medici-predicted standard deviation of Vtw and associated Ioff-based yield due to the RDF of NSD(x,y) in the Lg = 18nm LP and HP DG FinFETs

4-1 Comparison of UFDG-predicted fT of an Lg = 28nm DG FinFET having a G-S/D overlap, with that of FinFETs having G-S/D underlap optimized for low-power and high-frequency RF applications

5-1 Taurus-predicted characteristics of Lg = 25nm (= Leff) FD/SOI nMOSFETs with midgap gate and tSi = 6nm

5-2 Taurus-predicted characteristics, vs. tSi, of Lg = 25nm thin-BOX/GP nMOSFETs with

2.5nm G-S/D underlap and midgap gate

5-3 Taurus-predicted characteristics, vs. VGP, of Lg = 25nm thin-BOX/GP nMOSFETs with

2.5nm G-S/D underlap and midgap gate

5-4 Taurus-predicted characteristics, vs. Leff, of thin-BOX/GP nMOSFETs with VGP for strong accumulation and controlled DIBL





5-5 Taurus-predicted characteristics, vs. Leff, of thin-BOX/GP nMOSFETs with VGP for strong accumulation

5-6 Taurus-predicted LP and HP scaling limits defined by tSi = 5nm, for thin-BOX/GP MOSFETs and DG nFinFETs

–  –  –

1-1 Structure of a FinFET with gate wrapped over the vertical fin, forming two sidewall gates.

2-1 Results of calibrating UFDG to an undoped Lg = 60nm DG pFinFET (fin aspect ratio hSi/ tSi = 100nm/17nm), with and without DICE

2-2 Illustration of a DG MOSFET biased in the saturation region, showing the body/channel divided into a gradual channel and a high-field portion

2-3 UFDG-predicted gradual-channel length, relative to Lg = 18nm, versus drain voltage for a DG nMOSFET, with and without DICE

2-4 Medici-predicted inversion-electron density across the UTB at the virtual source of a simple 18nm DG nMOSFET for low and high drain voltages

2-5 UFDG-predicted drain current versus voltage characteristics, with and without DICE, of an 18nm DG nMOSFET

2-6 UFDG- and MEDICI-predicted drain current versus voltage characteristics of the 18nm DG nMOSFET

2-7 UFDG-predicted drain current versus voltage characteristics, with and without DICE, for the 18nm DG nMOSFET, but with the proper series resistance, mobility, and velocityovershoot modeling

2-8 UFDG-predicted gate capacitance versus voltage characteristics of the 18nm DG nMOSFET at low and high drain voltages, with and without DICE

2-9 UFDG/Spice3-predicted output voltage transient of a two-stage 18nm DG CMOS inverter chain, with the input voltage pulsing shown to reveal the (pull-down plus pull-up) propagation delay

3-1 S/D-extension lateral doping profiles in an undoped DG FinFET, showing variable encroachment into the channel

3-2 Measured (a) strong-inversion and (b) subthreshold current-voltage characteristics of two Lg = 70nm undoped DG nFinFETs, which have different NSD(y) due to variations in the S/ D processing

3-3 UFDG-predicted (a) subthreshold and (b) strong-inversion current-voltage characteristics of the 18nm LP and HP DG FinFETs

3-4 The DG FinFET structure showing how the S/D-extension and channel regions were partitioned to account for the RDF of NSD(x,y) in the Medici domain

4-1 UFDG-predicted gDS of a 28nm DG FinFET

4-2 UFDG-predicted CG (normalized to hSi) versus VGS at VDS = 1.2V, with and without G-S/ D underlap

4-3 UFDG-predicted gm versus Lg of DG FinFETs with an abrupt S/D doping profile.........64 4-4 UFDF-predicted gDS versus Lg for the FinFETs, with and without consideration of quasiballistic limit

4-5 UFDG-predicted Avo versus Lg of DG FinFETs.

4-6 UFDG-predicted fT versus Lg of DG FinFETs

Basic thin-BOX FD/SOI nMOSFET structure, with P+ GP

5-1 5-2 Taurus-predicted weak-inversion characteristics of a thin-BOX device along with UFDG calibration

5-3 Comparison of Taurus-predicted IDS-VGS characteristics of thin-BOX FD/SOI devices w/ and w/o GP

5-4 Comparison of Taurus-predicted IDS-VGS characteristics of thin-BOX FD/SOI nMOSFET with that of DG nFinFET

–  –  –

UTB Ultra-Thin Body UFDG University of Florida Double-Gate SCE Short-Channel Effect DIBL Drain-Induced Barrier Lowering DICE Drain-Induced Charge Enhancement QM Quantum-Mechanical SDE Source/Drain Extension

–  –  –

Chair: Jerry G. Fossum Major: Electrical and Computer Engineering This dissertation seeks to understand the unique physics of, to explore non-conventional ways of designing, and to gain insights on the performance of nanoscale double-gate (DG) MOSFETs, particularly the quasi-planar FinFET structure. Our work includes modeling of draininduced charge enhancement, suggesting a novel way of adjusting the threshold voltage of nanoscale DG MOSFETs via limited source/drain dopants in the channel, comparing the analog/ RF performance of DG FinFETs and bulk-silicon MOSFETs, and studying and designing ultrathin-BOX FD/SOI MOSFETs with comparisons to DG FinFETs.

Drain-induced charge enhancement (DICE) is a short-channel effect which is unique to nanoscale DG MOSFETs with undoped bodies because of their significantly high carrier mobility.

We model this effect, and study its effect on the current, charge, capacitance, and transcapacitance of DG MOSFETs. We find that DICE is a beneficial effect because it increases current without significantly affecting gate capacitance.

Adjusting the threshold voltage of DG MOSFETs with undoped bodies for low-power and high-performance applications is a challenging task. We propose a design approach in which limited densities of source/drain dopants in the channel can be used to effect an adjustment of threshold voltage in DG MOSFETs, while maintaining low sensitivities to random-doping fluctuations.

Most of the current literature on the analog/RF performance of DG MOSFETs is based on experimental results, with little physics-based explanation of the results. We give physical insights on the design and performance of DG MOSFETs for analog/RF applications, and compare them with bulk-silicon MOSFETs. We find that like for digital applications, DG MOSFETs have superior analog performance than that of conventional planar bulk-silicon MOSFETs.

Recently, there has emerged a considerable interest in planar FD/SOI MOSFETs with ultra-thin BOX. We give our physical insights, based on device simulations, on the design and performance of ultra-thin-BOX FD/SOI MOSFETs, and check their scalability toward the end of the CMOS roadmap compared with DG FinFETs.

–  –  –

Scaling conventional MOSFETs, i.e., bulk-silicon and partially depleted (PD)/SOI MOSFETs, to gate lengths (Lg) ~40nm has become increasingly challenging because the channel-doping density required has become very high. Conventional MOSFETs rely on channeldoping density to control threshold voltage (Vt) and short-channel effects (SCEs). As these devices are scaled, the latter are controlled by reducing the depletion width by increasing channeldoping density. For Lg ~40nm, the required channel-doping density has become so high that the variation in Vt due to random variations in the channel-doping density has become a serious issue.

At such short Lg, reliable control of channel doping density is virtually impossible. Under this scenario, double-gate (DG) MOSFETs, e.g. FinFETs, have emerged as a most promising candidate to replace the bulk-Si MOSFET [1]. The primary advantage of the FinFET is the excellent control of SCEs [2] without relying on channel doping, which makes it potentially scalable to the end of the SIA ITRS roadmap [1]. Since FinFETs rely on undoped ultra-thin bodies (UTB) to control SCEs, random variations in threshold voltage (Vt) and other device characteristics due to process variations can be greatly reduced [3]. In Fig. 1.1 we show the basic structure of a FinFET. The gate is wrapped over the thin vertical fin, forming two sidewall gates.

The top of the fin could be gated, forming a triple-gate device [4], but we focus on the DG structure which is more pragmatic [2].

DG-FinFET technology has not yet received complete acceptance by the integratedcircuits manufacturing companies because of some of the challenges associated with the DGFinFET technology like higher cost of SOI wafers, control of the nanoscale fin, and lack of reliable ways of engineering the source/drain doping profile. Higher cost of SOI wafers has led to some interest in the bulk-Si FinFETs [5], [6]. However, due to significantly high, controlled substrate-doping density required to suppress source/drain-leakage current, and need to precisely match the depth of source and drain regions to the substrate doping, the viability of bulk-Si FinFETs is doubtful [7]. In order to scale DG FinFETs to the end of the roadmap, reliable ways of engineering the source/drain profile will have to be developed. This task is particularly challenging because the UTB thickness tends to be about 5nm near the scaling limit of Lg. The diffusion of source/drain dopants through such thin bodies is not well understood. As we will show through comprehensive studies in this dissertation, DG FinFETs tend to have significantly better performance for both digital and analog/RF applications. But, in order for DG FinFETs to replace bulk-Si MOSFETs, the technological challenges like those mentioned here will have to be overcome.



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